1. Field of the Invention
The invention relates to data-processing systems, and more particularly, to a communication mechanism for use in a high-performance, parallel-processing system.
2. Description of the Prior Art
The above-referenced U.S. Pat. No. 5,113,523, describes a parallel processor comprised of a plurality of processing nodes, each node including a processor and a memory. Each processor includes means for executing instructions, logic means connected to the memory for interfacing the processor with the memory and means for internode communication. The internode communication means connect the nodes to form a first array of order n having a hypercube topology. A second array of order n having nodes connected together in a hypercube topology is interconnected with the first array to form an order n+1 array. The order n+1 array is made up of the first and second arrays of order n, such that a parallel processor system may be structured with any number of processors that is a power of two. A set of I/O processors are connected to the nodes of the arrays by means of I/O channels. The means for internode communication comprises a serial data channel driven by a clock that is common to all of the nodes.
In U.S. Pat. No. 4,729,095 of Colley et al granted Mar. 1, 1988 and assigned to Ncube Corporation, there is described a broadcast pointer instruction having a source operand which is the address in memory of a message to be broadcast to a number of processors. The broadcast pointer instruction also includes a destination operated which is a multibit mask. A mask register is connected to output channel registers such that every bit position in the mask register that is set to a predetermined value will allow the corresponding output channel address register to be loaded. Decoding means load the mask register with the mask bits of the destination operand of the broadcast pointer instruction. A broadcast count instruction is provided including a source operand which is a plural bit integer equal to the number of bytes in the message. The broadcast count instruction includes a destination operand which is a multibit mask. As transmission progresses, the address register is incremented and the count is decremented by the number of bytes transferred.
The prior art apparatus requires software controls to set up data paths, route data to nodes over the paths created, and remove paths that are no longer in service,
It is a primary object of the present invention to provide a new communication mechanism for use in parallel processing system that will provide for communication path creation, data transmission over the created path, and path removal without the need for an external control.